1. Technical Field of the Invention
The invention concerns circuits presenting interconnection layers and specifically the manufacture of capacitors in such layers.
2. Description of Related Art
Some integrated circuits present a silicon substrate on which a multitude of transistors are formed. These circuits present several interconnection layers superimposed on the substrate in which the passive components are arranged such as capacitors. Such capacitor formation typically includes a metallic deposit and it's shaping by the classic stages of masking and chemical etching.
FIGS. 1 and 2 schematically illustrate known circuit cross-sections including a MIM type capacitor (Metal-Insulator-Metal). Passivation layers have not been represented for reasons of legibility. These capacitors are realized by means of metallic deposits in an interconnection layer of the circuit. These capacitors are specifically used as a decoupling capacitance of an integrated circuit, as a coupling capacitance for impedance matching or as a radio frequency capacitance device. The silicon surface used by such capacitors is relatively important and therefore implies a significant cost.
FIG. 1 illustrates a planar capacitor. The circuit presents an insulator layer 1 integral with the substrate. One lower electrode 2 is arranged on the insulator layer 1. The lower electrode 2 is covered by an insulator layer 3, this layer 3 is itself covered by an upper electrode 4. The planar capacitor is realized at the same level as an interconnection line 5 on the insulator layer 1. The insulator layer 3 and electrodes 2 and 4 are flat.
FIG. 2 illustrates a three-dimensional capacitor. Electrodes 2 and 4 and the insulator layer 3 show relief, in order to increase surface density capacitance of the capacitor. The electrodes and layer 3 are thus formed in grooves of layer 1.
According to one manufacturing process of these two types of capacitor, electrodes 2 and 4 and insulator layer 3 are executed by stacking beforehand three layers by successive full plate deposition on insulator layer 1. The edge of the capacitor is then delimited by means of a mask and an etching of the three stacked layers. Since a similar stage of masking and etching is used to delimit the three layers, the capacitor edge is essentially perpendicular to layer 1.
Such a process presents drawbacks. Some capacitors formed in this way can present defects. A premature stressing or a leakage current can thus be generated between the upper electrode and the lower electrode. Etching residues such as the conductor polymers specifically can accumulate at the capacitor's edge. Defects induced by the etching can also lead to short-circuit. The miniaturization of capacitors leads to a reduced thickness of the insulator 3 layer. The risk of stress or current leakage is then further increased.
According to another manufacturing process, electrodes 2 and 4 as well as the insulator layer 3 are realized by previously stacking three successive layers of full plate deposits on insulator layer 1. A first edge is delimited by a first mask and by a first etching of layer 4. A second edge is delimited by a second mask and by a second etching of layers 3 and 2. FIG. 3 illustrates the edge of the capacitor obtained this way. The first edge thus delimits the upper electrode 4. The second edge delimits the lower electrode 2 and the insulator layer 3. The upper electrode 4 is therefore recessed with respect to the lower electrode 2. In addition, the electrodes are then separated by the surface of the insulator layer 3 between the two edges. The accidental short-circuit risk is thus considerably reduced.
In certain configurations a part of the lower electrode is used as interconnection metal. Three-dimensional capacitors currently use electrodes of reduced thickness in order to increase the surface density of the grooves. When the electrode thickness is very reduced, the lower electrode does not form a sufficiently thick interconnection metal and an additional interconnection line 5 is necessary. Interconnection lines are also used for the connection of the upper or lower layer components.
FIG. 4 illustrates a metallic deposit 6 formed on the capacitor. By masking and etching we seek to obtain the structure of FIG. 3. FIGS. 5 and 6 illustrate known defects of the capacitor obtained by such a process. In FIG. 5 the etching of the interconnection line 5 is insufficient and allows a parasitic metal deposit 7 to subsist between the edges of electrodes 2 and 4. This deposit 7 can generate a parasitic capacitance or a short-circuit between electrodes. On FIG. 6 the etching of the interconnection 5 line is excessive and suppresses the insulator layer 3 between the edges of electrodes 2 and 4. A short-circuit can then be formed between electrodes on the capacitor's edge, for example by a parasitic spacer formed by the conductor polymers. The number of photolithography stages is also increased, which raises the cost of the manufacturing process.